LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.dec_pkg.all;
entity dec_op is
	port(
		   clk 		:in std_ulogic;
		   rst		:in std_ulogic;
		   cal_len :in frame_length;
		   state :out std_ulogic;
		  ppin_flag	:in std_ulogic;					--raddr_flag = '1' denote the ping bank  else  pang bank
		 	ppout_flag	:in std_ulogic;					--waddr_flag = '1' denote the ping bank  else  pang bank	
		 	request	:in std_ulogic;       -- the start signal 
		 	ack    :out std_ulogic;                
		 	op_end		:out std_ulogic;             
			uin		:in word16_array;
		 	chin		:in word16_array;
		 	sigin :in word16;
		 	read :out std_ulogic;
		-- 	r_en: out std_ulogic_vector(7 downto 0);
		-- 	rch_en: out std_ulogic_vector(7 downto 0);
		 	write :out std_ulogic;
		 --	w_en :out std_ulogic_vector(7 downto 0);
		 	addr :out std_ulogic_vector(8 downto 0);
		 
		 	wb_clk    :in std_ulogic;
		  wb_en     :in std_ulogic;
		  wb_addr   :in word16;
		  wb_data   :in word16;
		  debug_en : in std_ulogic;
      debug_clk : out std_ulogic;
      debug_sel : in std_ulogic;
      debug_data: out std_ulogic_vector(31 downto 0);
		 	dout_op		:out word32_array
		     );
end entity;


architecture rtl  of dec_op is
	component v1col is port (
		clk :in  std_ulogic;
	        
	        state1 : in std_ulogic;
                wb_clk :in  std_ulogic;
	              wb_en  : in std_ulogic;
	              sel8   : in std_ulogic_vector(3 downto 0);
                wb_addr :in std_ulogic_vector(7 downto 0);
                wb_data :in std_ulogic_vector(7 downto 0); 
                enable :in std_ulogic;
                vup_length : in frame_length;
	              b_len : in block_length; 
                cup16_end :in std_ulogic;
                vup_enable : in std_ulogic;
                count_vr : in std_ulogic_vector(6 downto 0);	
		            e1 : in word32;
	              e2 : in word32;
		            e3 : in word32;
                e4 : in word32;
	        e5 : in word32;
	        e6 : in word32;
	        e7 : in word32;
	        e8 : in word32;
	        q1 : out word32;
	        q2 : out word32;
	        q3 : out word32;
	        q4 : out word32;
	        q5 : out word32;
	        q6 : out word32;
	        q7 : out word32;
	        q8 : out word32;
	        b  : out word32
	);
	end component;
	

	component op_control is  port (
    	rst : in std_ulogic;
	clk : in std_ulogic;
	request : in std_ulogic;
        cup_outflag : in std_ulogic; 
	
	cup_enable2: out std_ulogic;
	vup_enable2 : out std_ulogic;
	cup1_beginning : out std_ulogic;
	cup16_end2: out std_ulogic;
        read :out std_ulogic;
	--r_en : out std_ulogic_vector(7 downto 0);
	write :out std_ulogic;
	--w_en :out std_ulogic_vector(7 downto 0);
       state12 :out  std_ulogic;
	ack : out std_ulogic;
        ppin_flag : in std_ulogic;
	ppout_flag: in std_ulogic;
	op_end :out std_ulogic;
	addr : out std_ulogic_vector(8 downto 0);
	count_cr2 : out std_ulogic_vector(7 downto 0);
	count_cw2 : out std_ulogic_vector(7 downto 0);
  count_vr2 : out std_ulogic_vector(6 downto 0);
	count_vw2 : out std_ulogic_vector(6 downto 0);
	count_jw2 : out std_ulogic_vector(6 downto 0);
	wenr1 : out  std_ulogic_vector(7 downto 0);
	wenr2 : out  std_ulogic_vector(7 downto 0);
	wenr3 : out  std_ulogic_vector(7 downto 0);
	wenr4 : out  std_ulogic_vector(7 downto 0);
	wenr5 : out  std_ulogic_vector(7 downto 0);
	wenr6 : out  std_ulogic_vector(7 downto 0);
	wenr7 : out  std_ulogic_vector(7 downto 0);
	wenr8 : out  std_ulogic_vector(7 downto 0);
	bl : out integer range 50 to 512 ;
	enablex : out std_ulogic_vector(7 downto 0);
	wb_clk : in std_ulogic;
	wb_en : in std_ulogic;
	wb_addr : in std_ulogic_vector(15 downto 0);
  wb_data :  in std_ulogic_vector(15 downto 0);
  wb_en2 : out std_ulogic;
  wb_addr2 : out std_ulogic_vector(15 downto 0);
  wb_data2 : out std_ulogic_vector(15 downto 0)
	); 
	end component;



-------------------------------------------------------------------------
component cup_ram is port (
clk : in std_ulogic;
rst :in std_ulogic;
cup1_beginning :in std_ulogic;
state1 : in std_ulogic;
u :in  std_ulogic_vector(15 downto 0);
ch :in  std_ulogic_vector(15 downto 0);
sig : in std_ulogic_vector(15 downto 0);
count_cr :in  std_ulogic_vector(7 downto 0);
count_cw :in  std_ulogic_vector(7 downto 0);
count_vr : in std_ulogic_vector(6 downto 0);
count_vw : in std_ulogic_vector(6 downto 0);
cup_enable : in std_ulogic;
vup_enable : in std_ulogic;
wb_clk : in std_ulogic;
wenr    : in  std_ulogic_vector(7 downto 0);
--wenw    :  in std_ulogic_vector(7 downto 0);
wb_addr : in std_ulogic_vector(7 downto 0);
wb_data :in  std_ulogic_vector(7 downto 0);
e_temp :out  word32_array;
llrq :in word32_array;
debug_en : in std_ulogic;
debug_clk : out std_ulogic;
debug_sel : in std_ulogic;
debug_data: out std_ulogic_vector(31 downto 0);
cup_outflag :out  std_ulogic
);
end  component ;


component cup_ram1 is port (
clk : in std_ulogic;
rst :in std_ulogic;
state1 : in std_ulogic;
cup1_beginning :in std_ulogic;
u :in  std_ulogic_vector(15 downto 0);
ch :in  std_ulogic_vector(15 downto 0);
sig : in std_ulogic_vector(15 downto 0);
count_cr :in  std_ulogic_vector(7 downto 0);
count_cw :in  std_ulogic_vector(7 downto 0);
count_vr : in std_ulogic_vector(6 downto 0);
count_vw : in std_ulogic_vector(6 downto 0);
cup_enable : in std_ulogic;
vup_enable : in std_ulogic;
wb_clk : in std_ulogic;
wenr    : in  std_ulogic_vector(7 downto 0);
--wenw    :  in std_ulogic_vector(7 downto 0);
wb_addr : in std_ulogic_vector(7 downto 0);
wb_data :in  std_ulogic_vector(7 downto 0);
e_temp :out  word32_array;
llrq :in word32_array
);
end  component ;


component cup_ram2 is port (
clk : in std_ulogic;
rst :in std_ulogic;
state1 : in std_ulogic;
cup1_beginning :in std_ulogic;
u :in  std_ulogic_vector(15 downto 0);
ch :in  std_ulogic_vector(15 downto 0);
sig : in std_ulogic_vector(15 downto 0);
count_cr :in  std_ulogic_vector(7 downto 0);
count_cw :in  std_ulogic_vector(7 downto 0);
count_vr : in std_ulogic_vector(6 downto 0);
count_vw : in std_ulogic_vector(6 downto 0);
cup_enable : in std_ulogic;
vup_enable : in std_ulogic;
wb_clk : in std_ulogic;
wenr    : in  std_ulogic_vector(7 downto 0);
--wenw    :  in std_ulogic_vector(7 downto 0);
wb_addr : in std_ulogic_vector(7 downto 0);
wb_data :in  std_ulogic_vector(7 downto 0);
e_temp :out  word32_array;
llrq :in word32_array
);
end  component ;


component cup_ram3 is port (
clk : in std_ulogic;
rst :in std_ulogic;
state1 : in std_ulogic;
cup1_beginning :in std_ulogic;
u :in  std_ulogic_vector(15 downto 0);
ch :in  std_ulogic_vector(15 downto 0);
sig : in std_ulogic_vector(15 downto 0);
count_cr :in  std_ulogic_vector(7 downto 0);
count_cw :in  std_ulogic_vector(7 downto 0);
count_vr : in std_ulogic_vector(6 downto 0);
count_vw : in std_ulogic_vector(6 downto 0);
cup_enable : in std_ulogic;
vup_enable : in std_ulogic;
wb_clk : in std_ulogic;
wenr    : in  std_ulogic_vector(7 downto 0);
--wenw    :  in std_ulogic_vector(7 downto 0);
wb_addr : in std_ulogic_vector(7 downto 0);
wb_data :in  std_ulogic_vector(7 downto 0);
e_temp :out  word32_array;
llrq :in word32_array
);
end  component ;


component cup_ram4 is port (
clk : in std_ulogic;
rst :in std_ulogic;
cup1_beginning :in std_ulogic;
state1 : in std_ulogic;
u :in  std_ulogic_vector(15 downto 0);
ch :in  std_ulogic_vector(15 downto 0);
sig : in std_ulogic_vector(15 downto 0);
count_cr :in  std_ulogic_vector(7 downto 0);
count_cw :in  std_ulogic_vector(7 downto 0);
count_vr : in std_ulogic_vector(6 downto 0);
count_vw : in std_ulogic_vector(6 downto 0);
cup_enable : in std_ulogic;
vup_enable : in std_ulogic;
wb_clk : in std_ulogic;
wenr    : in  std_ulogic_vector(7 downto 0);
--wenw    :  in std_ulogic_vector(7 downto 0);
wb_addr : in std_ulogic_vector(7 downto 0);
wb_data :in  std_ulogic_vector(7 downto 0);
e_temp :out  word32_array;
llrq :in word32_array
);
end  component ;


component cup_ram5 is port (
clk : in std_ulogic;
rst :in std_ulogic;
cup1_beginning :in std_ulogic;
state1 : in std_ulogic;
u :in  std_ulogic_vector(15 downto 0);
ch :in  std_ulogic_vector(15 downto 0);
sig : in std_ulogic_vector(15 downto 0);
count_cr :in  std_ulogic_vector(7 downto 0);
count_cw :in  std_ulogic_vector(7 downto 0);
count_vr : in std_ulogic_vector(6 downto 0);
count_vw : in std_ulogic_vector(6 downto 0);
cup_enable : in std_ulogic;
vup_enable : in std_ulogic;
wb_clk : in std_ulogic;
wenr    : in  std_ulogic_vector(7 downto 0);
--wenw    :  in std_ulogic_vector(7 downto 0);
wb_addr : in std_ulogic_vector(7 downto 0);
wb_data :in  std_ulogic_vector(7 downto 0);
e_temp :out  word32_array;
llrq :in word32_array
);
end  component ;


component cup_ram6 is port (
clk : in std_ulogic;
rst :in std_ulogic;
cup1_beginning :in std_ulogic;
state1 : in std_ulogic;
u :in  std_ulogic_vector(15 downto 0);
ch :in  std_ulogic_vector(15 downto 0);
sig : in std_ulogic_vector(15 downto 0);
count_cr :in  std_ulogic_vector(7 downto 0);
count_cw :in  std_ulogic_vector(7 downto 0);
count_vr : in std_ulogic_vector(6 downto 0);
count_vw : in std_ulogic_vector(6 downto 0);
cup_enable : in std_ulogic;
vup_enable : in std_ulogic;
wb_clk : in std_ulogic;
wenr    : in  std_ulogic_vector(7 downto 0);
--wenw    :  in std_ulogic_vector(7 downto 0);
wb_addr : in std_ulogic_vector(7 downto 0);
wb_data :in  std_ulogic_vector(7 downto 0);
e_temp :out  word32_array;
llrq :in word32_array
);
end  component ;


component cup_ram7 is port (
clk : in std_ulogic;
rst :in std_ulogic;
cup1_beginning :in std_ulogic;
state1 : in std_ulogic;
u :in  std_ulogic_vector(15 downto 0);
ch :in  std_ulogic_vector(15 downto 0);
sig : in std_ulogic_vector(15 downto 0);
count_cr :in  std_ulogic_vector(7 downto 0);
count_cw :in  std_ulogic_vector(7 downto 0);
count_vr : in std_ulogic_vector(6 downto 0);
count_vw : in std_ulogic_vector(6 downto 0);
cup_enable : in std_ulogic;
vup_enable : in std_ulogic;
wb_clk : in std_ulogic;
wenr    : in  std_ulogic_vector(7 downto 0);
--wenw    :  in std_ulogic_vector(7 downto 0);
wb_addr : in std_ulogic_vector(7 downto 0);
wb_data :in  std_ulogic_vector(7 downto 0);
e_temp :out  word32_array;
llrq :in word32_array
);
end  component ;



--------------------------------------------------------------------------

	signal b_len	: block_length ;					--default:  block length 50;
	signal f_len	: frame_length ;					--default:  frame length 400;
  signal vup_length :frame_length ; --default :vup rate adaption 400;
  signal half_blen : integer ; 

-------------cup and vup  finish flag-------------------------------
signal cup_finish_flag :std_ulogic;
signal vup_finish_flag :std_ulogic;
signal judge_finish_flag :std_ulogic;
-------------the cup and vup count reg --------------------------
signal count_cr,count_cw: std_ulogic_vector(7 downto 0);
signal count_vr,count_vw,count_jw: std_ulogic_vector(6 downto 0);
signal vcnt,jcnt:std_logic_vector(2 downto 0);
------------the first cup and last cup-----------------------------
signal cup1_beginning:std_ulogic;
signal cup16_end:std_ulogic;

-----------the cup vup write flag ----------------------------------------
signal cup_outflag  :std_ulogic;
signal vup_outflag  :std_ulogic;
signal voutflag     : std_ulogic;
signal judge_outflag     :std_ulogic;
------------the cup vup enable flag ----------------------------------------
signal cup_enable   :std_ulogic;
signal vup_enable   :std_ulogic;
------------------iteration count ----------------------------
signal iteration_count : std_ulogic_vector(4 downto 0);
-------------------------------------------vup  read and write addreaa
signal vupads11,vupads21,vupads31,vupads41,vupads51,vupads61,vupads71,vupads81:std_ulogic_vector(15 downto 0);
signal vupads12,vupads22,vupads32,vupads42,vupads52,vupads62,vupads72,vupads82:std_ulogic_vector(15 downto 0);
signal vupads13,vupads23,vupads33,vupads43,vupads53,vupads63,vupads73,vupads83:std_ulogic_vector(15 downto 0);
signal vupads14,vupads24,vupads34,vupads44,vupads54,vupads64,vupads74,vupads84:std_ulogic_vector(15 downto 0);
signal vupads15,vupads25,vupads35,vupads45,vupads55,vupads65,vupads75,vupads85:std_ulogic_vector(15 downto 0);
signal vupads16,vupads26,vupads36,vupads46,vupads56,vupads66,vupads76,vupads86:std_ulogic_vector(15 downto 0);
signal vupads17,vupads27,vupads37,vupads47,vupads57,vupads67,vupads77,vupads87:std_ulogic_vector(15 downto 0);
signal vupads18,vupads28,vupads38,vupads48,vupads58,vupads68,vupads78,vupads88:std_ulogic_vector(15 downto 0);

-------------------------------------------------------------------------------
type array1_type is array (7 downto 0) of std_ulogic_vector (15 downto 0);
type array2_type is array (7 downto 0)  of array1_type;
type array1_addr is array  (7 downto 0 )  of std_ulogic_vector(7 downto 0);
type array2_addr is array (7 downto 0)  of array1_addr;
type word16_16matrix is array (7 downto 0)of word32_array;

signal wenr1 ,wenr2 ,wenr3,wenr4,wenr5,wenr6,wenr7,wenr8 : std_ulogic_vector(7 downto 0);
--signal wenw1 ,wenw2,wenw3,wenw4,wenw5 ,wenw6,wenw7,wenw8: std_ulogic_vector(7 downto 0);
----------------------------------------------------------------------------
signal wen : std_ulogic_vector(127 downto 0) ;
signal enablev : std_ulogic_vector(7 downto 0);
signal e_temp :word16_16matrix;---reg the signal to vup
signal llrq   :word16_16matrix;---reg the signal from vup

----------the output address ---------------------------------------
signal sigmax,sigmay : std_ulogic_vector(15 downto 0);
signal count_temp,judge_count_temp: std_ulogic_vector(6 downto 0);
signal uinx		: word16_array;
signal chinx		: word16_array;
signal ack1,state1: std_ulogic;	
signal x	,y :std_ulogic;
signal wb_en1 :  std_ulogic;
signal wb_addr1 :  std_ulogic_vector(15 downto 0);
signal wb_data1 :  std_ulogic_vector(15 downto 0) ;
begin




-------------------------------------------------------------
process (clk,rst)
  begin 
    if rst = '0' then 
     elsif clk'event and clk = '1' then 
       
       state <= state1;
     end if;
end process;
       

-----------------------------------addr generator-----------------------------
----------------------------------------------------------------------------




--process (clk)
--  begin 
--    if clk'event and clk = '1' then
--    if state1 = '0' then 
--       sigmay <= sigin;
--       vup_length <= cal_len;
--     end if;
--   end if;
-- end process;
  
          op_c : op_control port map (
	  rst => rst ,
	  clk => clk ,
	  request => request ,
	  cup_outflag => cup_outflag,
	  cup_enable2 => cup_enable ,
	  vup_enable2 => vup_enable,
	  cup1_beginning => cup1_beginning,
          cup16_end2 => cup16_end,
	  read  => read ,
	 -- r_en => r_en ,
	  write => write,
	 -- w_en => w_en ,
    state12 => state1,
    ack => ack ,
    ppin_flag => ppin_flag ,
    ppout_flag => ppout_flag ,
    op_end => op_end,
	  addr => addr,
	  count_cr2 => count_cr ,
	  count_cw2 => count_cw ,
	  count_vr2 => count_vr ,
	  count_vw2 => count_vw,
          count_jw2 => count_jw,
          wenr1 => wenr1 ,
          wenr2 => wenr2 ,
          wenr3 => wenr3 ,
          wenr4 => wenr4 ,
          wenr5 => wenr5 ,
          wenr6 => wenr6 ,
          wenr7 => wenr7 ,
          wenr8 => wenr8 ,
	  bl => b_len,
	  enablex => enablev,
    wb_clk => wb_clk,
	  wb_en => wb_en,
 	  wb_addr => wb_addr,
	  wb_data => wb_data,
	  wb_en2 => wb_en1,
	  wb_addr2 => wb_addr1,
	  wb_data2 => wb_data1
	);


						  
 -----------------------------------------generate cup and memory bank--------------------------------
           c1 : cup_ram port map (
                       clk => clk ,
                       rst =>rst,
                       cup1_beginning => cup1_beginning ,
                       u      => uin(0),
                       sig => sigin ,
                       ch => chin(0),
                       state1 => state1,
                       count_cr => count_cr ,
                       count_cw => count_cw ,
                       count_vr => count_vr ,
                       count_vw => count_vw ,
                       cup_enable => cup_enable ,
                       vup_enable => vup_enable ,
                       wb_clk => wb_clk ,
                       wenr => wenr1,
                      -- wenw => wenw1,
                       wb_addr => wb_addr1(7 downto 0),
                       wb_data => wb_data1(7 downto 0),
                       e_temp => e_temp(0),
                       llrq => llrq(0),
                       debug_clk => debug_clk,
                       debug_en => debug_en ,
                       debug_sel => debug_sel,
                       debug_data => debug_data,
                       cup_outflag => cup_outflag );
        
          c2 : cup_ram1 port map (
                       clk => clk ,
                       rst =>rst,
                       cup1_beginning => cup1_beginning ,
                       u      => uin(1),
                       sig => sigin ,
                       state1 => state1,
                       ch => chin(1),
                       count_cr => count_cr ,
                       count_cw => count_cw ,
                       count_vr => count_vr ,
                       count_vw => count_vw ,
                       cup_enable => cup_enable ,
                       vup_enable => vup_enable ,
                       wb_clk => wb_clk ,
                       wenr => wenr2,
                    --   wenw => wenw2,
                       wb_addr => wb_addr1(7 downto 0),
                       wb_data => wb_data1(7 downto 0),
                       e_temp => e_temp(1),
                       llrq => llrq(1) );

            c3 : cup_ram2 port map (
                       clk => clk ,
                       rst =>rst,
                       cup1_beginning => cup1_beginning ,
                       u      => uin(2),
                       sig => sigin,
                       ch => chin(2),
                       state1 => state1,
                       count_cr => count_cr ,
                       count_cw => count_cw ,
                       count_vr => count_vr ,
                       count_vw => count_vw ,
                       cup_enable => cup_enable ,
                       vup_enable => vup_enable ,
                       wb_clk => wb_clk ,
                       wenr => wenr3,
                     --  wenw => wenw3,
                       wb_addr => wb_addr1(7 downto 0),
                       wb_data => wb_data1(7 downto 0),
                       e_temp => e_temp(2),
                       llrq => llrq(2) );
           c4 : cup_ram3 port map (
                       clk => clk ,
                       rst =>rst,
                       cup1_beginning => cup1_beginning ,
                       u      => uin(3),
                       sig => sigin ,
                       ch => chin(3),
                       state1 => state1,
                       count_cr => count_cr ,
                       count_cw => count_cw ,
                       count_vr => count_vr ,
                       count_vw => count_vw ,
                       cup_enable => cup_enable ,
                       vup_enable => vup_enable ,
                       wb_clk => wb_clk ,
                       wenr => wenr4,
                      -- wenw => wenw4,
                       wb_addr => wb_addr1(7 downto 0),
                       wb_data => wb_data1(7 downto 0),
                       e_temp => e_temp(3),
                       llrq => llrq(3) );
            c5 : cup_ram4 port map (
                       clk => clk ,
                       rst =>rst,
                       cup1_beginning => cup1_beginning ,
                       u      => uin(4),
                       sig => sigin ,
                       ch => chin(4),
                       state1 => state1,
                       count_cr => count_cr ,
                       count_cw => count_cw ,
                       count_vr => count_vr ,
                       count_vw => count_vw ,
                       cup_enable => cup_enable ,
                       vup_enable => vup_enable ,
                       wb_clk => wb_clk ,
                       wenr => wenr5,
                     --  wenw => wenw5,
                       wb_addr => wb_addr1(7 downto 0),
                       wb_data => wb_data1(7 downto 0),
                       e_temp => e_temp(4),
                       llrq => llrq(4) );
          c6 : cup_ram5 port map (
                       clk => clk ,
                       rst =>rst,
                       cup1_beginning => cup1_beginning ,
                       u      => uin(5),
                       sig => sigin ,
                       ch => chin(5),
                       state1 => state1,
                       count_cr => count_cr ,
                       count_cw => count_cw ,
                       count_vr => count_vr ,
                       count_vw => count_vw ,
                       cup_enable => cup_enable ,
                       vup_enable => vup_enable ,
                       wb_clk => wb_clk ,
                     wenr => wenr6,
                       --wenw => wenw6,
                       wb_addr => wb_addr1(7 downto 0),
                       wb_data => wb_data1(7 downto 0),
                       e_temp => e_temp(5),
                       llrq => llrq(5) );
         c7 : cup_ram6 port map (
                       clk => clk ,
                       rst =>rst,
                       cup1_beginning => cup1_beginning ,
                       u      => uin(6),
                       state1 => state1,
                       sig => sigin ,
                       ch => chin(6),
                       count_cr => count_cr ,
                       count_cw => count_cw ,
                       count_vr => count_vr ,
                       count_vw => count_vw ,
                       cup_enable => cup_enable ,
                       vup_enable => vup_enable ,
                       wb_clk => wb_clk ,
                       wenr => wenr7,
                      -- wenw => wenw7,
                       wb_addr => wb_addr1(7 downto 0),
                       wb_data => wb_data1(7 downto 0),
                       e_temp => e_temp(6),
                       llrq => llrq(6) );
           c8 : cup_ram7 port map (
                       clk => clk ,
                       rst =>rst,
                       cup1_beginning => cup1_beginning ,
                       u      => uin(7),
                       state1 => state1,
                       sig => sigin ,
                       ch => chin(7),
                       count_cr => count_cr ,
                       count_cw => count_cw ,
                       count_vr => count_vr ,
                       count_vw => count_vw ,
                       cup_enable => cup_enable ,
                       vup_enable => vup_enable ,
                       wb_clk => wb_clk ,
                       wenr => wenr8,
                     --  wenw => wenw8,
                       wb_addr => wb_addr1(7 downto 0),
                       wb_data => wb_data1(7 downto 0),
                       e_temp => e_temp(7),
                       llrq => llrq(7) );




----------------------------------------------------------------------------------------
-----------------------------------------------------------generate vup ----------------
v1 : v1col port map(
clk => clk,
wb_clk  => wb_clk,
wb_en => wb_en1 ,
sel8 => wb_addr1(14 downto 11),
wb_addr => wb_addr1(7 downto 0) ,
wb_data => wb_data1(7 downto 0),
state1 => state1,
vup_length => cal_len,
b_len => b_len ,
enable => enablev(0),
cup16_end => cup16_end,
vup_enable => vup_enable,
count_vr => count_vr,
e1 => e_temp(0)(0),
e2 => e_temp(1)(0),
e3 => e_temp(2)(0),
e4 => e_temp(3)(0),
e5 => e_temp(4)(0),
e6 => e_temp(5)(0),
e7 => e_temp(6)(0),
e8 => e_temp(7)(0),
q1 => llrq(0)(0),
q2 => llrq(1)(0),
q3 => llrq(2)(0),
q4 => llrq(3)(0),
q5 => llrq(4)(0),
q6 => llrq(5)(0),
q7 => llrq(6)(0),
q8 => llrq(7)(0),
b => dout_op(0)
);
v2 : v1col port map(
clk => clk,

wb_clk  => wb_clk,
wb_en => wb_en1 ,
sel8 => wb_addr1(14 downto 11),
wb_addr => wb_addr1(7 downto 0) ,
wb_data => wb_data1(7 downto 0),
enable => enablev(1),
state1 => state1,
vup_length => cal_len,
b_len => b_len ,
cup16_end => cup16_end,
vup_enable => vup_enable,
count_vr => count_vr,
e1 => e_temp(0)(1),
e2 => e_temp(1)(1),
e3 => e_temp(2)(1),
e4 => e_temp(3)(1),
e5 => e_temp(4)(1),
e6 => e_temp(5)(1),
e7 => e_temp(6)(1),
e8 => e_temp(7)(1),
q1 => llrq(0)(1),
q2 => llrq(1)(1),
q3 => llrq(2)(1),
q4 => llrq(3)(1),
q5 => llrq(4)(1),
q6 => llrq(5)(1),
q7 => llrq(6)(1),
q8 => llrq(7)(1),
b => dout_op(1)
);
v3 : v1col port map(
clk => clk,

wb_clk  => wb_clk,
wb_en => wb_en1 ,
sel8 => wb_addr1(14 downto 11),
wb_addr => wb_addr1(7 downto 0) ,
wb_data => wb_data1(7 downto 0),
enable => enablev(2),
state1 => state1,
vup_length => cal_len,
b_len => b_len ,
cup16_end => cup16_end,
vup_enable => vup_enable,
count_vr => count_vr,
e1 => e_temp(0)(2),
e2 => e_temp(1)(2),
e3 => e_temp(2)(2),
e4 => e_temp(3)(2),
e5 => e_temp(4)(2),
e6 => e_temp(5)(2),
e7 => e_temp(6)(2),
e8 => e_temp(7)(2),
q1 => llrq(0)(2),
q2 => llrq(1)(2),
q3 => llrq(2)(2),
q4 => llrq(3)(2),
q5 => llrq(4)(2),
q6 => llrq(5)(2),
q7 => llrq(6)(2),
q8 => llrq(7)(2),
b => dout_op(2)
);
v4 : v1col port map(
clk => clk,

wb_clk  => wb_clk,
wb_en => wb_en1 ,
sel8 => wb_addr1(14 downto 11),
wb_addr => wb_addr1(7 downto 0) ,
wb_data => wb_data1(7 downto 0),
enable => enablev(3),
state1 => state1,
vup_length => cal_len,
b_len => b_len ,
cup16_end => cup16_end,
vup_enable => vup_enable,
count_vr => count_vr,
e1 => e_temp(0)(3),
e2 => e_temp(1)(3),
e3 => e_temp(2)(3),
e4 => e_temp(3)(3),
e5 => e_temp(4)(3),
e6 => e_temp(5)(3),
e7 => e_temp(6)(3),
e8 => e_temp(7)(3),
q1 => llrq(0)(3),
q2 => llrq(1)(3),
q3 => llrq(2)(3),
q4 => llrq(3)(3),
q5 => llrq(4)(3),
q6 => llrq(5)(3),
q7 => llrq(6)(3),
q8 => llrq(7)(3),
b => dout_op(3)
);
v5 : v1col port map(
clk => clk,

wb_clk  => wb_clk,
wb_en => wb_en1 ,
sel8 => wb_addr1(14 downto 11),
wb_addr => wb_addr1(7 downto 0) ,
wb_data => wb_data1(7 downto 0),
enable => enablev(4),
state1 => state1,
vup_length => cal_len,
b_len => b_len ,
cup16_end => cup16_end,
vup_enable => vup_enable,
count_vr => count_vr,
e1 => e_temp(0)(4),
e2 => e_temp(1)(4),
e3 => e_temp(2)(4),
e4 => e_temp(3)(4),
e5 => e_temp(4)(4),
e6 => e_temp(5)(4),
e7 => e_temp(6)(4),
e8 => e_temp(7)(4),
q1 => llrq(0)(4),
q2 => llrq(1)(4),
q3 => llrq(2)(4),
q4 => llrq(3)(4),
q5 => llrq(4)(4),
q6 => llrq(5)(4),
q7 => llrq(6)(4),
q8 => llrq(7)(4),
b => dout_op(4)
);	
v6 : v1col port map(
clk => clk,

wb_clk  => wb_clk,
wb_en => wb_en1 ,
sel8 => wb_addr1(14 downto 11),
wb_addr => wb_addr1(7 downto 0) ,
wb_data => wb_data1(7 downto 0),
enable => enablev(5),
state1 => state1,
vup_length => cal_len,
b_len => b_len ,
cup16_end => cup16_end,
vup_enable => vup_enable,
count_vr => count_vr,
e1 => e_temp(0)(5),
e2 => e_temp(1)(5),
e3 => e_temp(2)(5),
e4 => e_temp(3)(5),
e5 => e_temp(4)(5),
e6 => e_temp(5)(5),
e7 => e_temp(6)(5),
e8 => e_temp(7)(5),
q1 => llrq(0)(5),
q2 => llrq(1)(5),
q3 => llrq(2)(5),
q4 => llrq(3)(5),
q5 => llrq(4)(5),
q6 => llrq(5)(5),
q7 => llrq(6)(5),
q8 => llrq(7)(5),
b => dout_op(5)
);	
v7 : v1col port map(
clk => clk,

wb_clk  => wb_clk,
wb_en => wb_en1 ,
sel8 => wb_addr1(14 downto 11),
wb_addr => wb_addr1(7 downto 0) ,
wb_data => wb_data1(7 downto 0),
enable => enablev(6),
state1 => state1,
vup_length => cal_len,
b_len => b_len ,
cup16_end => cup16_end,
vup_enable => vup_enable,
count_vr => count_vr,
e1 => e_temp(0)(6),
e2 => e_temp(1)(6),
e3 => e_temp(2)(6),
e4 => e_temp(3)(6),
e5 => e_temp(4)(6),
e6 => e_temp(5)(6),
e7 => e_temp(6)(6),
e8 => e_temp(7)(6),
q1 => llrq(0)(6),
q2 => llrq(1)(6),
q3 => llrq(2)(6),
q4 => llrq(3)(6),
q5 => llrq(4)(6),
q6 => llrq(5)(6),
q7 => llrq(6)(6),
q8 => llrq(7)(6),
b => dout_op(6)
);

v8 : v1col port map(
clk => clk,

wb_clk  => wb_clk,
wb_en => wb_en1 ,
sel8 => wb_addr1(14 downto 11),
wb_addr => wb_addr1(7 downto 0) ,
wb_data => wb_data1(7 downto 0),
enable => enablev(7),
state1 => state1,
vup_length => cal_len,
b_len => b_len ,
cup16_end => cup16_end,
vup_enable => vup_enable,
count_vr => count_vr,
e1 => e_temp(0)(7),
e2 => e_temp(1)(7),
e3 => e_temp(2)(7),
e4 => e_temp(3)(7),
e5 => e_temp(4)(7),
e6 => e_temp(5)(7),
e7 => e_temp(6)(7),
e8 => e_temp(7)(7),
q1 => llrq(0)(7),
q2 => llrq(1)(7),
q3 => llrq(2)(7),
q4 => llrq(3)(7),
q5 => llrq(4)(7),
q6 => llrq(5)(7),
q7 => llrq(6)(7),
q8 => llrq(7)(7),
b => dout_op(7)
);
end rtl;
